1. Field of the Invention
The present invention is directed generally to semiconductors and more specifically to a method for producing a semiconductor layer structure having a planarized surface and the use thereof in the manufacture of bipolar transistors and DRAMS.
2. Description of the Related Art
The planarization of the surface of a semiconductor layer structure is becoming more significant with increasing miniaturization of microelectronic circuit structures and with the increasing use of multi-layer wirings. The reduced focus depth in sub-.mu.m lithography requires a far-reaching planarization of the surface of a semiconductor layer structure after every process step. Independently of these lithography problems, a planarization of the surface of a semiconductor layer structure during the process management is advantageous, since the adhesion of lacquer or other residues of materials at corners and edges is thereby avoided.
The term "local planarization" has become common usage in the literature when a planarity at the surface is satisfied only for specific structure sizes. When the planarity is satisfied for all structures over the entire surface of the semiconductor layer structure, then the term used is "global planarization".
For planarization of the surface of a semiconductor layer structure, it is known to apply a planarization layer that compensates for the irregularities in the surface by flowing (see, for example, A. Nagy et al, Solid State Techn., Jan. 1991, pages 53-56). The planarization layer is usually applied onto an insulating layer, particularly onto an intermediate oxide layer or a passivation layer. The surface of the semiconductor layer structure is prepared for following process steps by etching the planarization layer back. The planarization layer is thereby maximally etched back to such an extent that the surface of the insulating layer is uncovered in the region of the highest structures. However, interspaces between structures having this height remain filled with the material of the planarization layer.
The planarization that can be achieved in this method is dependent on the flow length of the lacquer or the oxide of the planarization layer. Commonly employed lacquers or oxides have flow lengths between 10 .mu.m and 200 .mu.m. When the surface to be planarized has larger structures than the flow length, then the thickness of the planarization layer on larger structures is increased, since a compensation by flowing only occurs in the region of the edge of the structures. These irregularities in the planarization layer are transferred into the surface in the following etch-back.
In order to avoid such irregularities, it has been proposed (see, for example, A. Nagy et al, Solid State Techn., Jan. 1991, pages 53 through 56 and V. Comello, 28/Semiconductor International, March 1990) to produce filler structures in larger regions free of structures before the deposition of the planarization layer. These filler structures are produced, for example, of photoresist by using an additional photo technique. Thus, only small interspaces that need be filled by flowing are present between the structures. Only a slight flowing of the planarization layer is required due to the reduction in the expanse of the interspaces. Since standard insulating layers are usually deposited with more or less conformal edge coverage, an additional mask that must be matched to the geometrical arrangement of the structures and to the thickness of the insulating layer is necessary for producing the filler structures. The filler structures must be formed of a material that can be etched with the same etching rate as the insulating layer.
Another known planarization method is polishing with chemical-mechanical erosion that is also referred to as chemical mechanical polishing (CMP) and that, for example, is known from V. Comello 28/Semiconductor International, March 1990 and Y. Hayashi et al, Ext. Abst. of Int. Conf. on Solid State Dev. and Mat., Business Center for Acad. Soc. Japan, XXVIII, pages 533-535, 1992. A polishing agent is thereby applied onto the surface to be planarized and is mechanically polished with a polishing disk. Raised structures having a smaller expanse are thereby eroded more greatly than structures having a greater expanse. (See Y. Hayashi et al, Ext. Abst. of Int. Conf. on Solid State Dev. and Mat., Business Center for Acad. Soc. Japan, XXVIII, pages 533 through 535, 1992).
Due to the finite stiffness of polishing disks, concavities occur in larger regions free of structures in chemical mechanical polishing (see C,W. Kaanta et al, VMIC Conference IEEE, June 1991, pages 144 through 152). In order to avoid these, it has been proposed in Y. Hayashi et al, Ext. Abst. of Int. Conf. on Solid State Dev. and Mat., Business Center for Acad. Soc. Japan, XXVIII, pages 533 through 535, 1992, to first apply a planarization layer for planarization with which a preplanarization is undertaken by flowing and etch-back. Then to achieve the final global planarization, chemical mechanical polishing is used.
The present invention provides a method for producing a semiconductor layer structure having a planarized surface with which irregularities in the region of larger structures as well as larger structure-free regions are avoided. In particular, the method should be suitable for use in the manufacture of bipolar transistors and DRAMS.
In the method of the invention, an insulating layer whose thickness is greater than the maximum step height is applied onto the surface of a semiconductor layer structure that has elevations having a height up to a maximum step height. The insulating layer is subsequently structured such that it has irregularities in the region of the edges of the elevations. These irregularities have essentially the same lateral expanse. Subsequently, irregularities are planarized by chemical mechanical polishing and/or deposition, flowing and etch-back of a planarization layer. Only these irregularities need be planarized in the method of the invention. The expanse of the irregularities is dependent on the size of the elevations and on the spacing between neighboring elevations. The problems that derive in known methods in the planarization of surfaces having larger structures and larger structure-free regions are therefore avoided.
For structuring the insulating layer, it lies within the scope of the invention to apply a stop layer having essentially conformal edge coverage under the insulating layer and to apply an auxiliary layer onto the insulating layer. Thus, the insulating layer can be selectively etched both relative to the auxiliary layer as well as to the stop layer. Openings are produced in the auxiliary layer above the elevations, and the expanses of these openings are less than or equal to the expanse of the elevations and the surface of the insulating layer being uncovered in them. The structuring of the insulating layer then occurs selectively relative to the auxiliary layer and relative to the stop layer in an isotropic etching process. The auxiliary layer is removed after the structuring of the insulating layer.
The openings in the auxiliary layer are preferably formed by using a photolithographic process, whereby an auxiliary mask is used. The auxiliary mask essentially has the same structures with inverse contrast as a mask used in the manufacture of the elevations. The structures in the auxiliary mask are at most as large as those in the mask. It is advantageous to diminish the size of the structures in the auxiliary mask by a reserve corresponding to the alignment tolerance of the mask.
It lies within the scope of the invention to implement the isotropic etching process at least until the surface of the stop layer is reached inside the openings. Peaks that project beyond the level of the insulating layer thereby occur at the edges of the elevations. These can be effectively planarized thereafter by chemical mechanical polishing.
According to another embodiment of the invention, the isotropic etching process is implemented at least until an oxide thickness of d.sub.ox =h+h/2+D has been etched, whereby h is the thickness of the insulating layer and D is the alignment precision with which the openings are produced relative to the elevations. In this case, the insulating layer is etched back until no peaks of the insulating layer remain above the maximum step height. Since the isotropic etching process attacks selectively relative to the auxiliary layer and relative to the stop layer, an under-etching is formed under the auxiliary layer.
Also it lies within the scope of the invention to apply a further insulating layer surface-wide after the removal of the auxiliary layer. This further insulating layer is provided with an essentially planar surface by using chemical polishing and/or by deposition, flowing and etch-back of a planarization layer. In this embodiment, too, only structures having the lateral expanse of the under-etching need be planarized.
The method is especially suited for the planarization of the surface of a semiconductor layer structure having a microelectronic circuit. The microelectronic circuit is particularly realized in a silicon substrate or in an SOI substrate. In this case, the insulating layer is at least part of an intermediate oxide layer that is essentially SiO.sub.2. In this case, the stop layer has Si.sub.3 N.sub.4 at least at its surface. The stop layer is preferably formed as a double layer of SiO.sub.2 and an Si.sub.3 N.sub.4 layer. In this case, the auxiliary layer is preferably polysilicon.
The method is quite versatile. In particular, it can be used in the manufacture of bipolar transistors. After the formation of the planar surface, an opening on a semiconductor surface is thereby produced in the insulating layer, and the active transistor regions are produced in this semiconductor surface by selective epitaxy.
Another advantageous use of the present invention is in the manufacture of a DRAM having shallow trench insulation.
The invention shall be set forth in greater detail below with reference to the figures and to an exemplary embodiment.